Video and Vision Processing Suite Intel® FPGA IP User Guide
ID
683329
Date
9/30/2021
Public
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About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide
Generating a Video and Vision Processing IP
To include the IP in a design, generate the IP in Platform Designer.
- Create a New Intel® Quartus® Prime project
- Open Platform Designer and create a project.
The video and vision processing IPs are only available in Platform Designer.
- Select DSP > Vision and Video Processing > <IP name> Intel® FPGA IP and click Add
- Enter a name for your IP variant and click Create.
The name is for both the top-level RTL module and the corresponding .ip file.The parameter editor for this IP appears.
- Choose your parameters.
- Click Generate HDL.
Intel® Quartus® Prime generates the RTL and the files necessary to instantiate the IP in your design and synthesize it.