Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2021

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Document Table of Contents

3D LUT IP Latency

The latency information can predict the approximate latency between the input and the output of your video processing pipeline.
Table 15.  3D LUT IP operation mode latencyThe table shows latency as a number of valid clock cycles. Intel measures the latency assuming that other functions on the datapath are not stalling the IP, i.e. the output ready signal is high.
Device Latency (cycles)

Intel Arria 10

Intel Cyclone 10 GX


Intel Agilex

Intel Stratix 10