Video and Vision Processing Suite Intel® FPGA IP User Guide
ID
683329
Date
9/30/2021
Public
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About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide
Warp IP Performance and Resource Utilization
Intel provides resource and utilization data for guidance. The designs target an Intel Arria 10 10AX115N2F40I2LG device.
PIxel in parallel | Bits per Color Sample | Number of Engines | Maximum Video Width 1 | Memory Buffer Size | ALMs | Memory Blocks (M20K) | DSP Blocks |
---|---|---|---|---|---|---|---|
1 | 10 | 1 | 2048 | HD | ~7,000 | 253 | 36 |
PIxel in parallel | Bits per Color Sample | Number of Engines | Max Video Width 2 | Memory Buffer Size | ALMs | Memory Blocks (M20K) | DSP Blocks |
---|---|---|---|---|---|---|---|
1 | 10 | 1 | 3840 | UHD | ~7,000 | 389 | 36 |
PIxel in parallel | Bits per Color Sample | Number of Engines | Max Video Width3 | Memory Buffer Size | ALMs | Memory Blocks (M20K) | DSP Blocks |
---|---|---|---|---|---|---|---|
2 | 10 | 2 | 3840 | UHD | ~10,000 | 465 | 72 |
1 Same maximum video width for input and output.
2 Same maximum video width for input and output.
3 Same maximum video width for input and output.