Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 3/28/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Report Metastability

The Timing Analyzer’s Reports > Clock Domain Crossings > Report Metastability... command generates a list of synchronization register chains found in the design, and can provide estimates of the Mean Time Between Failures (MTBF) of each chain. The equivalent scripting command is report_metastability.

Metastable registers have outputs hovering at a voltage between high and low for a length of time beyond the normal tCO for the register, which may cause subsequent registers that use this metastable signal to latch different values. Synchronize register chains when transferring data between unrelated clock domains to reduce the probability of the captured data signal becoming metastable.

A synchronization register chain is a sequence of registers with the same clock, that is driven by a pin, or logic from an unrelated clock domain. All but the last register in the chain must connect only to the next register, but may do so through logic.

The Metastability Report displays the following for each synchronization chain the analysis discovers:

  • Typical Mean Time Between Failures (MTBF) for the chain
  • Number of synchronization registers in the chain
  • Names of synchronization registers in the chain
  • Data toggle rate used in the MTBF estimation
  • Source clock domain names
  • Synchronization clock domain names