Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

3.6.5.2. Creating Virtual Clocks

A virtual clock is a clock without a real source in the design, or a clock that does not interact directly with the design. You can use virtual clocks in I/O constraints to represent clocks that drive external devices connected to the FPGA..

To create virtual clocks, use the create_clock constraint with no value for the <targets> option.

This following example defines a 100 MHz virtual clock because the command includes no <targets>.

create_clock -period 10 -name my_virt_clk

I/O Constraints with Virtual Clocks

You can use a base clock to constrain the circuit in the FPGA and a virtual clock to represent the clock driving the external device. .

Figure 96. Virtual Clock Board TopologyThe figure shows the base clock (system_clk), virtual clock (virt_clk), and output delay for the virtual clock constraints example

The following example creates the 10 ns virt_clk virtual clock, with a 50% duty cycle, with the first rising edge occurring at 0 ns. The virtual clock can then become the clock source for an output delay constraint.

Virtual Clock Constraints

#create base clock for the design
create_clock -period 5 [get_ports system_clk]
#create the virtual clock for the external register
create_clock -period 10 -name virt_clk
#set the output delay referencing the virtual clock
set_output_delay -clock virt_clk -max 1.5 [get_ports dataout]
set_output_delay -clock virt_clk -min 0.0 [get_ports dataout]