## Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 3/28/2022
Public

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## 3.6.8.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset

In this example, the source clock frequency is an integer multiple of the destination clock frequency and the destination clock has a positive phase offset. The source clock frequency is 5 ns and destination clock frequency is 10 ns. The destination clock also has a positive offset of 2 ns with respect to the source clock. The source clock frequency can be an integer multiple of the destination clock frequency with an offset when a PLL generates both clocks with different multiplication.
Figure 154. Source Clock Frequency is Multiple of Destination Clock Frequency with Offset

The following timing diagram shows the default setup check analysis the Timing Analyzer performs:

Figure 155. Setup Timing Diagram
Figure 156. Setup Check Calculation

The setup relationship in this example demonstrates that the data is not launched at edge one, and the data that is launched at edge three must be captured; therefore, you can relax the setup requirement. To correct the default analysis, you shift the launch edge by two clock periods with a start multicycle setup exception of three.

The following multicycle exception adjusts the default analysis in this example:

### Multicycle Constraint

set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \
-setup -start 3

The following timing diagram shows the preferred setup relationship for this example:

Figure 157. Preferred Setup Check Analysis

The Timing Analyzer performs the following calculation to determine the hold check:

Figure 158. Hold Check Calculation

The following timing diagram shows the default hold check analysis the Timing Analyzer performs for a start multicycle setup value of three:

Figure 159. Default Hold Check Analysis

In this example, the hold check two is too restrictive. The data is launched next by the edge at 10 ns and must check against the data captured by the current latch edge at 12 ns, which does not occur in hold check two. To correct the default analysis, you must specify a multicycle hold exception of one.