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2.2.6. Metastability Analysis
To minimize the failures due to metastability, circuit designers typically use a sequence of registers, also known as a synchronization register chain, or synchronizer, in the destination clock domain to resynchronize the data signals to the new clock domain.
The mean time between failures (MTBF) is an estimate of the average time between instances of failure due to metastability.
The Timing Analyzer analyzes the potential for metastability in your design and can calculate the MTBF for synchronization register chains. The Timing Analyzer then estimates the MTBF of the entire design from the synchronization chains the design contains.
In addition to reporting synchronization register chains found in the design, the Intel® Quartus® Prime software also protects these registers from optimizations that might negatively impact MTBF, such as register duplication and logic retiming. The Intel® Quartus® Prime software can also optimize the MTBF of your design if the MTBF is too low.
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