Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 3/28/2022
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3.6.8.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency

In this example, the destination clock frequency value of 5 ns is an integer multiple of the source clock frequency of 10 ns. The destination clock frequency can be an integer multiple of the source clock frequency when a PLL generates both clocks with a phase shift on the destination clock.

The following example shows a design in which the destination clock frequency is a multiple of the source clock frequency.

Figure 136. Destination Clock is Multiple of Source Clock

The following timing diagram shows the default setup check analysis that the Timing Analyzer performs:

Figure 137. Setup Timing Diagram
Figure 138. Setup Check Calculation

The setup relationship demonstrates that the data requires capture at edge two; therefore, you can relax the setup requirement. To correct the default analysis, you shift the latch edge by one clock period with an end multicycle setup exception of two. The following multicycle exception assignment adjusts the default analysis in this example:

Multicycle Constraint

set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \
     -setup -end 2

The following timing diagram shows the preferred setup relationship for this example:

Figure 139. Preferred Setup Analysis

The following timing diagram shows the default hold check analysis the Timing Analyzer performs with an end multicycle setup value of two.

Figure 140. Default Hold Check
Figure 141. Hold Check Calculation

In this example, hold check one is too restrictive. The data is launched by the edge at 0 ns and must check against the data captured by the previous latch edge at 0 ns, which does not occur in hold check one. To correct the default analysis, you must use an end multicycle hold exception of one.