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220.127.116.11. Report Fmax Summary
The Timing Analyzer computes fMAX for all paths where the same clock drives the source and destination registers or ports. The Timing Analyzer ignores paths of different clocks and generated clocks. For paths between a clock and its inversion, the Timing Analyzer computes fMAX as if the rising and falling edges scale along with fMAX, such that the duty cycle (in terms of a percentage) is maintained. You must constrain all clocks for accurate timing analysis.
The Restricted Fmax can indicate a "Limit due to hold check." Typically, hold checks do not limit the maximum frequency (fMAX) because these checks are for same-edge relationships, and therefore independent of clock frequency. An example of this occurs when launch equals zero and latch equals zero. However, with an inverted clock transfer, or a multicycle transfer (such as setup=2, hold=0), then the hold relationship is not a same-edge transfer and changes with the clock frequency.
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