Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

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ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

3.12.1. Selecting RDW Output Choices for Various Memory Blocks

The available output choices for the RDW behavior vary, depending on the types of RDW and embedded memory block in use.
Table 12.  Output Choices for the Same-Port and Mixed-Port Read-During-WriteThis table lists the available output choices for the same-port, and mixed-port RDW for various embedded memory blocks.
Memory Block Types Single-port RAM 7 Simple dual-port RAM 8 True dual-port RAM
Same port RDW Mixed-port RDW Same port RDW 9 Mixed-port RDW 10
M512 No parameter editor 11

Old Data

Don’t Care

N/A

M4K No parameter editor 11

Old Data

Don’t Care

M-RAM

Don’t Care

Don’t Care

MLAB

Don’t Care

New Data

12

New Data

13

Old Data

Don’t Care

N/A

MLAB is not supported in true dual-port RAM

M9K

Don’t Care

New Data

14

Old Data

Old Data

Don’t Care

New Data

14

Old Data

Old Data

Don’t Care

M144K

Old Data

Don’t Care

New Data

12

Old Data

Don’t Care

M10K

Don’t Care

New Data

12

Old Data

Don’t Care

New Data

12

Old Data

Don’t Care

M20K

Old Data

Don’t Care

Old Data

Don’t Care

New Data

12

Old Data

Don’t Care

LCs No parameter editor 11

Old Data

Don’t Care

N/A

Note: The RDW old data mode is not supported when the Error Correction Code (ECC) is engaged.
Note: If you are not concerned about the output when RDW occurs and would like to improve performance, you can select Don't Care. Selecting Don't Care increases the flexibility in the type of memory block being used, provided you do not assign block type when you instantiate the memory block.
7 Single-port RAM only supports same-port RDW, and the clocking mode must be either single clock mode, or input/output clock mode.
8 Simple dual-port RAM only supports mixed-port RDW, and the clocking mode must be either single clock mode, or input/output clock mode.
9 The clocking mode must be either single clock mode, input/output clock mode, or independent clock mode.
10 The clocking mode must be either single clock mode, or input/output clock mode.
11 There is no option page available from the parameter editor in this mode. By default, the new data flows through to the output.
12 The new data behavior for same-port RDW support NEW_DATA_NO_NBE_READ for x on masked byte only when the byte enable applies.
13 Only supported in single clock mode with new data behavior of NEW_DATA_NO_NBE_READ.
14 There are two types of new data behavior for same-port RDW that you can choose from the parameter editor. When byte enable is applied, you can choose to read old data, or ‘X’ on the masked byte. The respective parameter values are:
  • NEW_DATA_WITH_NBE_READ for old data on masked byte.
  • NEW_DATA_NO_NBE_READ for x on masked byte.
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