188.8.131.52. Arria 10 Transceiver Reconfiguration Interface
The Arria 10 transceiver reconfiguration interface provides access to the registers in the embedded Arria 10 Native PHY IP core. This interface provides direct access to the hard PCS registers on the device.
This interface is available only in variations that target an Arria 10 device. In variations that target an Arria V device or a Stratix V device, user logic reconfigures the transceivers through the transceiver reconfiguration controller, an external block that you must instantiate in your design outside the 50G Interlaken IP core.
The Arria 10 transceiver reconfiguration interface complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.
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