Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/01/2024
Document Table of Contents

3.5.1. Running Advanced I/O Timing

Advanced I/O timing analysis uses your board trace model and termination network specification to report accurate output buffer-to-pin timing estimates, FPGA pin and board trace signal integrity and delay values. Advanced I/O timing runs automatically for supported devices during compilation.