Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/01/2024
Document Table of Contents

3. Managing Device I/O Pins

This chapter describes efficient planning and assignment of I/O pins in your target device. Consider I/O standards, pin placement rules, and your PCB characteristics early in the design phase.

Figure 56.  Quartus® Prime Pin Planner GUI

Table 29.   Quartus® Prime I/O Pin Planning Tools

I/O Planning Task

Click to Access

Plan interfaces and device periphery Tools > Interface Planner

Edit, validate, or export pin assignments

Assignments > Pin Planner

For more information about special pin assignment features for the Arria® 10 SoC devices, refer to Instantiating the HPS Component in the Arria® 10 Hard Processor System Technical Reference Manual.