Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/01/2024
Document Table of Contents

1.1.4. Specifying Timing Constraints

You must specify timing constraints that describe the clock frequency requirements, timing exceptions, and I/O timing requirements of your design for comparison against actual conditions observed during timing analysis. You define timing constraints in one or more Synopsys* Design Constraints (.sdc) files that you add to the project.

You can specify timing constraints in the Timing Analyzer GUI, which automatically generates an .sdc based on your inputs. Click the Constraints menu in the Timing Analyzer to specify timing constraints that you can apply to your project.

Alternatively, you can create an initial .sdc with provided .sdc file templates, or manually in any text editor and then add the .sdc to the project.

In addition, generation of Intel FPGA IP or Platform Designer systems may also automatically generate and add to your project .sdc constraints.

Figure 6. Constraint menu in Timing Analyzer

When you specify a constraint in the GUI, the dialog box displays the equivalent SDC command syntax.

Create Clock Dialog Box

Individual timing assignments override project-wide requirements.

  • To avoid reporting incorrect or irrelevant timing violations, you can assign timing exceptions to nodes and paths.
  • The Timing Analyzer supports point-to-point timing constraints, wildcards to identify specific nodes when making constraints, and assignment groups to make individual constraints to groups of nodes.

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