Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/01/2024
Document Table of Contents

1. Constraining Designs

The design constraints, assignments, and logic options that you specify influence how the Quartus® Prime Compiler implements your design. The Compiler attempts to synthesize and place logic in a manner than meets your constraints. In addition, design constraints also have an impact on how the Timing Analyzer and the Power Analyzer influence synthesis, placement, and routing.

You can specify design constraints in the GUI, with scripts, or directly in the files that store the constraints. The Quartus® Prime software preserves the constraints that you specify in the GUI in the following files:

  • Quartus® Prime Settings file (<project_directory>/<revision_name>.qsf)—contains project-wide and instance-level assignments for the current revision of the project, in Tcl syntax. Each revision of a project has a separate .qsf file.
  • Synopsys* Design Constraints file (<project_directory>/<revision_name>.sdc)—the Timing Analyzer uses industry-standard Synopsys* Design Constraint format and stores those constraints in .sdc files.
By combining the syntax of the .qsf files and the .sdc files with procedural Tcl, you can automate iterations over several different settings, changing constraints and recompiling.

What's New In This Version

  • Applied initial Altera rebranding throughout.
  • Importing and Exporting I/O Pin Assignments topic is updated for current list of file formats supported.