Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/01/2024
Document Table of Contents

3.2.3. Assigning I/O Banks

Some Intel® FPGA devices support assignments to I/O banks. I/O banks are a logical grouping of I/O pins for convenience in making certain types of assignments, such as I/O standard assignments.

When targeting a device family that supports I/O bank assignments, the I/O Bank cell value automatically populates in Pin Planner once you select a corresponding pin Location. The rows for various I/O banks are color coded for easy visual identification.
Figure 58. Pin Location and I/O Bank Cells in Pin Planner

When you save your Pin Planner constraints, the pin location saves to the project .qsf that also saves the I/O bank locations as a comment. Command-line users can use this comment to identify I/O bank locations for the placed pins without launching the Quartus® Prime software GUI.

Figure 59. I/O Bank Location Saved As Comment in QSF