Quartus® Prime Pro Edition User Guide: Design Constraints
ID
683143
Date
7/07/2025
Public
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor
1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor
1.1.2.4. Specify I/O Constraints in Pin Planner
1.1.2.5. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.6. Adjust Constraints with the Chip Planner
1.1.2.7. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups
3.2.2. Assigning Slew Rate and Drive Strength
3.2.3. Assigning I/O Banks
3.2.4. Changing Pin Planner Highlight Colors
3.2.5. Showing I/O Lanes
3.2.6. Assigning Differential Pins
3.2.7. Entering Pin Assignments with Tcl Commands
3.2.8. Entering Pin Assignments in HDL Code
3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis
You can select a near-end or far-end point for I/O timing analysis. Near-end timing analysis extends to the device pin. You can apply the set_output_delay constraint during near-end analysis to account for the delay across the board.
With far-end I/O timing analysis, the advanced I/O timing analysis extends to the external device input, at the far-end of the board trace. Whether you choose a near-end or far-end timing endpoint, the board trace models are taken into account during timing analysis.