Quartus® Prime Pro Edition User Guide: Design Constraints
ID
683143
Date
7/07/2025
Public
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor
1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor
1.1.2.4. Specify I/O Constraints in Pin Planner
1.1.2.5. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.6. Adjust Constraints with the Chip Planner
1.1.2.7. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups
3.2.2. Assigning Slew Rate and Drive Strength
3.2.3. Assigning I/O Banks
3.2.4. Changing Pin Planner Highlight Colors
3.2.5. Showing I/O Lanes
3.2.6. Assigning Differential Pins
3.2.7. Entering Pin Assignments with Tcl Commands
3.2.8. Entering Pin Assignments in HDL Code
3.4. Validating Pin Assignments
The Quartus® Prime software validates I/O pin assignments against predefined I/O rules for your target device. You can use the following tools to validate your I/O pin assignments throughout the pin planning process:
Note: You must assign all I/Os in your design before you can generate a .sof file for programming the target device. Starting in Quartus® Prime Pro Edition version 25.1.1, the Assembler does not generate a .sof programming file during compilation unless all I/Os have location and I/O standard assignments. Previously, Quartus® Prime Pro Edition only issued a critical warning during the Fitter stage if a design lacks complete pin location and I/O standard assignments but still allowed .sof generation.
I/O Validation Tool |
Description |
Click to Run |
---|---|---|
Advanced I/O Timing |
Fully validates I/O assignments against all I/O and timing checks during compilation |
Processing > Start Compilation |