188.8.131.52. Specify Instance-Specific Constraints in Assignment Editor 184.108.40.206. Specify NoC Constraints in NoC Assignment Editor 220.127.116.11. Specify I/O Constraints in Pin Planner 18.104.22.168. Plan Interface Constraints in Interface Planner and Tile Interface Planner 22.214.171.124. Adjust Constraints with the Chip Planner 126.96.36.199. Constraining Designs with the Design Partition Planner
4.2.1. Assigning to Exclusive Pin Groups 4.2.2. Assigning Slew Rate and Drive Strength 4.2.3. Assigning I/O Banks 4.2.4. Changing Pin Planner Highlight Colors 4.2.5. Showing I/O Lanes 4.2.6. Assigning Differential Pins 4.2.7. Entering Pin Assignments with Tcl Commands 4.2.8. Entering Pin Assignments in HDL Code
3.2.2. Tile Interface Planner Tool Flow
The Tile Interface Planner user interface guides you through each step in the tile interface planning process.
Figure 31. Tile Interface Planner Tool Flow
- Step 1: Instantiate IP and Run Design Analysis—Tile Interface Planner first requires a design with component IP, targeting the Intel Agilex® 7 FPGA with F-tile. After initial design setup, you run Design Analysis to elaborate the component IP in the design.
- Step 2: Initialize Tile Interface Planner—launch Tile Interface Planner, component IP and existing assignment data loads, and the legality engine initializes.
- Step 3: Update Plan with Project Assignments—enable or disable any existing placement assignments and optionally load placement data from previous planning sessions for the current tile planning session.
- Step 4: Create a Tile Plan—use the Plan tab to locate the potential legal locations for each unplaced component IP, place the IP in the tile location, and verify that the placement is legal in real-time to ensure correlation in the final implementation.
- Step 5: Save Tile Plan Assignments—save the tile IP plan assignments to the project for design compilation.
- Step 6: Run Logic Generation and Design Synthesis—run the Compiler Logic Generation stage to implement your tile plan and continue synthesis and the remaining design compilation stages.