126.96.36.199. Specify Instance-Specific Constraints in Assignment Editor 188.8.131.52. Specify NoC Constraints in NoC Assignment Editor 184.108.40.206. Specify I/O Constraints in Pin Planner 220.127.116.11. Plan Interface Constraints in Interface Planner and Tile Interface Planner 18.104.22.168. Adjust Constraints with the Chip Planner 22.214.171.124. Constraining Designs with the Design Partition Planner
4.2.1. Assigning to Exclusive Pin Groups 4.2.2. Assigning Slew Rate and Drive Strength 4.2.3. Assigning I/O Banks 4.2.4. Changing Pin Planner Highlight Colors 4.2.5. Showing I/O Lanes 4.2.6. Assigning Differential Pins 4.2.7. Entering Pin Assignments with Tcl Commands 4.2.8. Entering Pin Assignments in HDL Code
126.96.36.199. Advanced I/O Timing Analysis Reports
The following reports show advanced I/O timing analysis information:
|I/O Timing Report
|Timing Analyzer Report
|Reports signal integrity and board delay data.
|Board Trace Model Assignments report
|Summarizes the board trace model component settings for each output and bidirectional signal.
|Signal Integrity Metrics report
|Contains all the signal integrity metrics calculated during advanced I/O timing analysis based on the board trace model settings for each output or bidirectional pin. Includes measurements at both the FPGA pin and at the far-end load of board delay, steady state voltages, and rise and fall times.
Note: By default, the Timing Analyzer generates the Slow‑Corner Signal Integrity Metrics report. To generate a Fast-Corner Signal Integrity Metrics report you must change the delay model by clicking Tools > Timing Analyzer.