3.1.3. Interface Planner NoC Tool Flow
You can use Interface Planner to assign physical locations for NoC initiators, targets (as part of the HBM2e or external memory interfaces), PLLs, and SSMs. If you do not make physical assignments for NoC elements, the Fitter places NoC elements automatically during compilation.
You use the floorplan view in Interface Planner to place hard memory NoC and periphery elements. There are three floorplan views available:
- NoC View—shows a filtered view of NoC initiators and targets.
- Chip View—shows the placeable locations for hard memory NoC elements, including NoC initiators, targets, PLLs, and SSMs.
- Package View—NoC elements are not visible in the Package View.
In the Chip View, the available NoC initiator and target locations appear as rows of small boxes across the top and bottom edges of the device, between the FPGA fabric and the periphery I/O structures. Placing your cursor over locations displays a tooltip indicating whether the location supports only an initiator, only a target, or both an initiator and a target.
The available NoC PLL and NoC SSM locations appear as smaller boxes at the end of the row of initiators and targets. The PLL and SSM locations appear at the left end of the rows (if using the Chip Top view), or at the right end of the rows (if using the Chip Bottom view).
Interface Planner Chip View, Closeup of NoC Features shows an example of the Interface Planner Chip View showing the top left corner of the die as viewed from the top. The two smaller pink boxes at the top left corner of the fabric are the locations of the NoC PLL and the NoC SSM.
In the NoC View, only the NoC initiators and targets are visible as larger rectangles. The targets and initiators for both high-speed NoC along the top edge of the die, and the high-speed NoC along the bottom edge of the die, are visible. Initiators and targets that may share the same location in the Chip View are split into separate elements in the NoC View.
The outer-top and outer-bottom rows are the targets for the top-edge NoC and bottom-edge NoC, respectively. Similarly, the inner-top and inner-bottom rows are the initiators for the top-edge NoC and bottom-edge NoC, respectively. As with the Chip View, if you place your cursor over one of these locations, a tooltip reports if that location supports a target or an initiator.
NoC View Showing Targets and Initiators is an example of the Interface Planner NoC View, showing the targets and initiators for both the top-edge NoC and the bottom-edge NoC.