126.96.36.199. Specify Instance-Specific Constraints in Assignment Editor 188.8.131.52. Specify NoC Constraints in NoC Assignment Editor 184.108.40.206. Specify I/O Constraints in Pin Planner 220.127.116.11. Plan Interface Constraints in Interface Planner and Tile Interface Planner 18.104.22.168. Adjust Constraints with the Chip Planner 22.214.171.124. Constraining Designs with the Design Partition Planner
4.2.1. Assigning to Exclusive Pin Groups 4.2.2. Assigning Slew Rate and Drive Strength 4.2.3. Assigning I/O Banks 4.2.4. Changing Pin Planner Highlight Colors 4.2.5. Showing I/O Lanes 4.2.6. Assigning Differential Pins 4.2.7. Entering Pin Assignments with Tcl Commands 4.2.8. Entering Pin Assignments in HDL Code
126.96.36.199. Flow Controls
The Flow control panel provides immediate access to common Tile Interface Planner commands from anywhere within Tile Interface Planner.
|Initialize Tile Interface Planner
|Launches the placement legality engine and loads the component IP and target device data that Design Analysis extracts.
|Opens the Assignments tab, which allows you to review and enable or disable any existing placement assignments for the current planning session.
|Optionally applies a previous tile planning session fixed placement assignments from the .qsf, and movable placements from a .json to the current tile interface plan.
|Opens the Plan tab for placing component IP in the tile interface plan.
|Opens the Save Assignments dialog box for saving the fixed tile constraints to the project .qsf and the movable building block constraints to a .json file.
Figure 54. Tile Interface Planner Flow Control