220.127.116.11. Specify Instance-Specific Constraints in Assignment Editor 18.104.22.168. Specify NoC Constraints in NoC Assignment Editor 22.214.171.124. Specify I/O Constraints in Pin Planner 126.96.36.199. Plan Interface Constraints in Interface Planner and Tile Interface Planner 188.8.131.52. Adjust Constraints with the Chip Planner 184.108.40.206. Constraining Designs with the Design Partition Planner
220.127.116.11. Step 1: Instantiate IP and Run Design Analysis 18.104.22.168. Step 2: Initialize Tile Interface Planner 22.214.171.124. Step 3: Update Plan with Project Assignments 126.96.36.199. Step 4: Create a Tile Plan Recommended Two-Stage Tile IP Placement 188.8.131.52. Step 5: Save Tile Plan Assignments 184.108.40.206. Step 6: Run Logic Generation and Design Synthesis
4.2.1. Assigning to Exclusive Pin Groups 4.2.2. Assigning Slew Rate and Drive Strength 4.2.3. Assigning I/O Banks 4.2.4. Changing Pin Planner Highlight Colors 4.2.5. Showing I/O Lanes 4.2.6. Assigning Differential Pins 4.2.7. Entering Pin Assignments with Tcl Commands 4.2.8. Entering Pin Assignments in HDL Code
220.127.116.11. Step 4: Create a Tile Plan
Click Plan Design on the Flow control to interactively place component IP in legal locations on device tiles. The Plan tab displays a hierarchical list of your project component IP design elements, alongside a graphical abstraction of the target device tile architecture. Place IP (and IP building blocks) in legal tile locations within the graphical tile floorplan.
Tile Interface Planner Design Elements and Chip View
Recommended Two-Stage Tile IP Placement
Handle IP tile placement in two stages for the most efficiency:
|Tile IP Placement||Description|
Note: Changes made in Tile Interface Planner do not apply to your Intel® Quartus® Prime project until you apply the generated tile interface plan constraints to your project, as Step 5: Save Tile Plan Assignments describes.