Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 10/02/2023
Public

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2.1.2.2. Specify NoC Constraints in NoC Assignment Editor

For designs targeting Intel Agilex® 7 M-Series FPGAs only, the NoC Assignment Editor in the Intel® Quartus® Prime Pro Edition software allows you to make logical assignments for hard memory NoC-related blocks in your design. These assignments include grouping, connectivity, address mapping, and bandwidth requirements.

The hard memory NoC facilitates high-bandwidth data movement between the FPGA core logic and memory resources, such as HBM2E and DDR5 memories. Refer to Interface Planner NoC Tool Flow and the Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide for details on the complete NoC flow including Interface Planner.

The Intel® Quartus® Prime software supports the following two flows for NoC design:

  • Platform Designer Connection Flow—you use Platform Designer to configure and instantiate your NoC-related IP. You also use Platform Designer to make connections between NoC initiator bridges and NoC target bridges and to define the addressing mapping for these connections. Once you generate HDL for your Platform Designer system, your design is ready for RTL simulation. You must use the NoC Assignment Editor to create additional assignments, such as specifying NoC groupings and optional performance targets. You can use Interface Planner to make physical location assignments for your NoC elements. Then you compile your design and review the results.
  • NoC Assignment Editor Connection Flow—you can configure and instantiate your NoC-related IP in either Platform Designer or directly in RTL. You then use the NoC Assignment Editor to make all NoC assignments including grouping, connectivity, address mapping, and optional performance targets. After completing the assignments and rerunning Analysis & Elaboration, your design is ready for RTL simulation. You can use Interface Planner to make physical location assignments for your NoC elements. Then compile your design and review the results.

Using the NoC Assignment Editor is similar to using the Assignment Editor, but the NoC Assignment Editor is optimized for making NoC assignments only. You must successfully complete Intel® Quartus® Prime Analysis & Elaboration before using the NoC Assignment Editor. After Analysis & Elaboration, you can access the NoC Assignment Editor by clicking Assignments > Network on Chip (NoC) Assignment Editor.

Specify assignments on the following NoC Assignment Editor tabs:

  • Group tab—specifies the Group Name of the NoC initiators and targets.
  • Connection tab—specifies the connections between NoC initiators and targets or SSM elements.
  • Attributes tab—specifies address mapping, bandwidth requirements, and transaction sizes for each connection.
Figure 2. Network on Chip (NoC) Assignment Editor Group Tab

The assignments made on the Group tab affect the assignments available in the Connection tab. The assignments made on the Connection tab affect the assignments available in the Attributes tab.

Complete the assignments on each tab in order before moving to the next tab.

After making assignments in the NoC Assignment Editor, you click Validate to validate the assignments, and then click Save to store the assignments in the Intel® Quartus® Prime settings file (.qsf).