188.8.131.52. Specify Instance-Specific Constraints in Assignment Editor 184.108.40.206. Specify NoC Constraints in NoC Assignment Editor 220.127.116.11. Specify I/O Constraints in Pin Planner 18.104.22.168. Plan Interface Constraints in Interface Planner and Tile Interface Planner 22.214.171.124. Adjust Constraints with the Chip Planner 126.96.36.199. Constraining Designs with the Design Partition Planner
4.2.1. Assigning to Exclusive Pin Groups 4.2.2. Assigning Slew Rate and Drive Strength 4.2.3. Assigning I/O Banks 4.2.4. Changing Pin Planner Highlight Colors 4.2.5. Showing I/O Lanes 4.2.6. Assigning Differential Pins 4.2.7. Entering Pin Assignments with Tcl Commands 4.2.8. Entering Pin Assignments in HDL Code
188.8.131.52. Step 5: Save Tile Plan Assignments
Once you have placed all IP components, and fixed any movable building blocks that you want to constrain, you save the constraints in Tile Interface Planner. Tile Interface Planner saves the fixed tile constraints to the project .qsf. The Compiler reads the .qsf assignments during the Logic Generation stage.
To save the tile plan assignments, follow these steps:
- Review and consider constraining any IP building blocks. To guarantee placement to exact locations, you must fix the IP building blocks connected to the IP pins to preserve those constraints in the .qsf, as Constraining IP Building Blocks describes.
Figure 42. Save Assignments from Tile Interface Planner
- In Tile Interface Planner, click Save Assignments on the Flow control, and then click OK.
- Close Tile Interface Planner and return to the Intel® Quartus® Prime GUI. The tile IP assignments are visible in the Assignment Editor (Assignments > Assignment Editor) and in the .qsf file.
Figure 43. Tile IP Assignments in Assignment Editor
- Run the Logic Generation stage, as Step 6: Run Logic Generation and Design Synthesis describes.