Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/03/2023

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2.2.1. Create a Project and Apply Constraints

The command-line executables include options for common global project settings and commands. You can use a Tcl script to apply constraints such as pin locations and timing assignments. You can write a Tcl constraint file, or generate one for an existing project by clicking Project > Generate Tcl File for Project.

The example creates a project with a Tcl script and applies project constraints using the tutorial design files in the < Intel® Quartus® Prime installation directory> /qdesigns/fir_filter/ directory.

project_new filtref -overwrite
# Assign family, device, and top-level file
set_global_assignment -name FAMILY "Arria 10"  
set_global_assignment -name DEVICE <Device>
set_global_assignment -name VERILOG_FILE filtref.v
# Assign pins
set_location_assignment -to clk Pin_28
set_location_assignment -to clkx2 Pin_29
set_location_assignment -to d[0] Pin_139
set_location_assignment -to d[1] Pin_140

Save the script in a file called setup_proj.tcl and type the commands illustrated in the example at a command prompt to create the design, apply constraints, compile the design, and perform fast-corner and slow-corner timing analysis. Timing analysis results are saved in two files, filtref_sta_1.rpt and filtref_sta_2.rpt.

quartus_sh -t setup_proj.tcl 
quartus_syn filtref 
quartus_fit filtref 
quartus_asm filtref 
quartus_sta filtref --model=fast --export_settings=off 
mv filtref_sta.rpt filtref_sta_1.rpt 
quartus_sta filtref --export_settings=off 
mv filtref_sta.rpt filtref_sta_2.rpt 

Type the following commands to create the design, apply constraints, and compile the design, without performing timing analysis:

quartus_sh -t setup_proj.tcl
quartus_sh --flow compile filtref

The quartus_sh --flow compile command performs a full compilation, and is equivalent to clicking the Start Compilation button in the toolbar.