Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

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ID 683143
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Constraining Designs 3. Interface Planning 4. Managing Device I/O Pins 5. Intel® Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Constraining Designs x
2.1. Specifying Design Constraints Designs in the GUI 2.2. Constraining Designs with Tcl Scripts 2.3. A Fully Iterative Scripted Flow 2.4. Constraining Designs Revision History
2.1. Specifying Design Constraints Designs in the GUI x
2.1.1. Global Constraints and Assignments 2.1.2. Node, Entity, and Instance-Level Constraints 2.1.3. Probing Between Components of the Intel® Quartus® Prime GUI 2.1.4. Specifying Timing Constraints in the GUI
2.1.2. Node, Entity, and Instance-Level Constraints x
2.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 2.1.2.2. Specify NoC Constraints in NoC Assignment Editor 2.1.2.3. Specify I/O Constraints in Pin Planner 2.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner 2.1.2.5. Adjust Constraints with the Chip Planner 2.1.2.6. Constraining Designs with the Design Partition Planner
2.1.2.1. Specify Instance-Specific Constraints in Assignment Editor x
2.1.2.1.1. Specifying Multi-Dimensional Bus Constraints
2.1.2.2. Specify NoC Constraints in NoC Assignment Editor x
2.1.2.2.1. NoC Assignment Editor Interface Controls
2.2. Constraining Designs with Tcl Scripts x
2.2.1. Create a Project and Apply Constraints 2.2.2. Assigning a Pin 2.2.3. Generating Intel® Quartus® Prime Settings Files 2.2.4. Synopsys* Design Constraint (.sdc) Files 2.2.5. Tcl-only Script Flows
3. Interface Planning x
3.1. Using Interface Planner 3.2. Using Tile Interface Planner 3.3. Interface Planning Revision History
3.1. Using Interface Planner x
3.1.1. Interface Planner User Interface 3.1.2. Interface Planner General Tool Flow 3.1.3. Interface Planner NoC Tool Flow 3.1.4. Interface Planner Reports
3.1.1. Interface Planner User Interface x
3.1.1.1. Flow Controls 3.1.1.2. Home Tab Controls 3.1.1.3. Assignments Tab Controls 3.1.1.4. Plan Tab Controls 3.1.1.5. Reports Tab Controls
3.1.2. Interface Planner General Tool Flow x
3.1.2.1. Step 1: Setup and Synthesize the Project 3.1.2.2. Step 2: Initialize Interface Planner 3.1.2.3. Step 3: Update Plan with Project Assignments 3.1.2.4. Step 4: Plan Periphery Placement 3.1.2.5. Step 5: Report Placement Data 3.1.2.6. Step 6: Validate and Export Plan Constraints
3.1.2.4. Step 4: Plan Periphery Placement x
3.1.2.4.1. Plan Clock Networks 3.1.2.4.2. Saving & Loading Floorplans
3.1.3. Interface Planner NoC Tool Flow x
3.1.3.1. Placing NoC Design Elements Using Interface Planner
3.1.3.1. Placing NoC Design Elements Using Interface Planner x
3.1.3.1.1. Recommended Placement Order for NoC Elements in Interface Planner 3.1.3.1.2. High-Speed Interconnect NoC Locations in Interface Planner
3.1.4. Interface Planner Reports x
3.1.4.1. Report Summary 3.1.4.2. Report Pins 3.1.4.3. Report HSSI Channels 3.1.4.4. Report Clocks 3.1.4.5. Report Periphery Locations 3.1.4.6. Report Cell Connectivity 3.1.4.7. Report Instance Assignments 3.1.4.8. Report NoC Performance
3.2. Using Tile Interface Planner x
3.2.1. Tile Interface Planner Terminology 3.2.2. Tile Interface Planner Tool Flow 3.2.3. Constraining Dynamic Reconfiguration IP 3.2.4. Tile Interface Planner GUI Reference
3.2.2. Tile Interface Planner Tool Flow x
3.2.2.1. Step 1: Instantiate IP and Run Design Analysis 3.2.2.2. Step 2: Initialize Tile Interface Planner 3.2.2.3. Step 3: Update Plan with Project Assignments 3.2.2.4. Step 4: Create a Tile Plan 3.2.2.5. Step 5: Save Tile Plan Assignments 3.2.2.6. Step 6: Run Logic Generation and Design Synthesis
3.2.2.4. Step 4: Create a Tile Plan x
3.2.2.4.1. Placing IP Components 3.2.2.4.2. Constraining IP Building Blocks
3.2.3. Constraining Dynamic Reconfiguration IP x
3.2.3.1. Defining a Dynamic Reconfiguration Group 3.2.3.2. Assigning Dynamic Reconfiguration Group Placement
3.2.4. Tile Interface Planner GUI Reference x
3.2.4.1. Flow Controls 3.2.4.2. Home Tab 3.2.4.3. Assignments Tab Controls 3.2.4.4. Plan Tab Controls 3.2.4.5. Tcl Console Window
3.2.4.4. Plan Tab Controls x
3.2.4.4.1. Design Tree and Filters 3.2.4.4.2. Reconfiguration Groups View 3.2.4.4.3. Legal Locations Pane
4. Managing Device I/O Pins x
4.1. I/O Planning Overview 4.2. Assigning I/O Pins 4.3. Importing and Exporting I/O Pin Assignments 4.4. Validating Pin Assignments 4.5. Verifying I/O Timing 4.6. Viewing Routing and Timing Delays 4.7. Scripting API 4.8. Managing Device I/O Pins Revision History
4.1. I/O Planning Overview x
4.1.1. Basic I/O Planning Flow 4.1.2. Integrating PCB Design Tools 4.1.3. Intel Device Terms
4.2. Assigning I/O Pins x
4.2.1. Assigning to Exclusive Pin Groups 4.2.2. Assigning Slew Rate and Drive Strength 4.2.3. Assigning Differential Pins 4.2.4. Entering Pin Assignments with Tcl Commands 4.2.5. Entering Pin Assignments in HDL Code
4.2.3. Assigning Differential Pins x
4.2.3.1. Overriding I/O Placement Rules on Differential Pins
4.2.5. Entering Pin Assignments in HDL Code x
4.2.5.1. Using Low-Level I/O Primitives
4.3. Importing and Exporting I/O Pin Assignments x
4.3.1. Importing and Exporting for PCB Tools 4.3.2. Migrating Assignments to Another Target Device
4.4. Validating Pin Assignments x
4.4.1. I/O Assignment Validation Rules 4.4.2. I/O Assignment Analysis 4.4.3. Understanding I/O Analysis Reports
4.4.2. I/O Assignment Analysis x
4.4.2.1. Early I/O Assignment Analysis Without Design Files 4.4.2.2. I/O Assignment Analysis With Design Files 4.4.2.3. Overriding Default I/O Pin Analysis
4.5. Verifying I/O Timing x
4.5.1. Running Advanced I/O Timing 4.5.2. Adjusting I/O Timing and Power with Capacitive Loading
4.5.1. Running Advanced I/O Timing x
4.5.1.1. Board Trace Models 4.5.1.2. Defining the Board Trace Model 4.5.1.3. Modifying the Board Trace Model 4.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 4.5.1.5. Advanced I/O Timing Analysis Reports
4.7. Scripting API x
4.7.1. Generate Mapped Netlist 4.7.2. Reserve Pins 4.7.3. Set Location 4.7.4. Exclusive I/O Group 4.7.5. Slew Rate and Current Strength
1. Answers to Top FAQs
2. Constraining Designs
3. Interface Planning
4. Managing Device I/O Pins
5. Intel® Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

3.1.2.4.1. Plan Clock Networks

Interface Planner allows you to visualize and plan clock networks. For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, you can locate, highlight, place, and edit the type of clock elements in the Plan tab.
Note: The Intel® Stratix® 10 device family does not support the Clocking filter in Interface Planner. For Intel® Stratix® 10 designs, use the Autoplace Selected command to place all unplaced clock elements.

Interface Planner generates a Clocks report that details the signals using low-skew routing networks (clock networks) in the device.

To identify and place clocking elements in your design, click the Clocking filter in the Plan tab. You can refine the list further by entering search text in the Design Element Filter. Interface Planner represents clock networks as groupings of the clock source, clock mux, and the clock region.

Figure 16. Clocking Design Elements

You can place an entire clock group or individual clock elements by dragging into the location, or using the Report Legal Locations of Selected Element or the Autoplace Selected commands. After placement, hover the cursor over the item in the Design Element list to highlight the placement. The placement of clock elements impacts the placement of dependent core and periphery elements.

You can edit the clock type for clocking design elements. The clock type impacts the placement of dependent core and periphery elements. Right-click any clock element to specify one of the available clock types.

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