- Updated What's New In This Version for NoC support and Intel Agilex 7 device family name changes.
- Updated Node, Entity, and Instance-Level Constraints topic for NoC Assignment Editor.
- Updated Plan Tab Controls topic for NoC View.
- Updated Reports Tab Controls topic for NoC Performance report.
- Added new Specify NoC Constraints in the NoC Assignment Editor topic.
- Added new NoC Assignment Editor Interface Controls topic.
- Updated product family name to "Intel Agilex 7."
- Added Top FAQs navigation to document cover.
- Added What's New In This Version section to Constraining Designs topic.
- Removed obsolete Tcl-only Timing Analysis topic.
- Updated Node, Entity, and Instance-Level Constraints topic for latest tools and Constraint Tools per Design Phase table.
- Revised Plan Interface Constraints topic for Tile Interface Planner.
- Revised Probing Between Components of the Intel® Quartus® Prime GUI for latest tools.
- Added "Specifying Multi-Dimensional Bus Constraints" topic.
- Updated examples in "Create a Project and Apply Constraints."
||Corrected minor typo in "Tcl-only Script Flows" topic.
- Clarified default location of .sdc and .qsf files in "Constraining Designs" topic.
- Added "Plan Interface Constraints with Interface Planner" topic.
- Added screenshots to "Constrain Designs with the Pin Planner" and "Constrain Designs with the Chip Planner."
- Added two new "Assigning a Pin" and "Creating a Project and Applying Constraints" topics showing Tcl examples.
- Added link to Using Timing Constraints topic in Timing Analyzer UG that explains all of the commands
- Renamed topic: Constraining Designs with the GUI to Constraining Designs with Quartus Prime Tools.
- Renamed topic: Global Constraints to Global Constraints and Assignments.
- Added table: Quartus Prime Tools to Set Global Constraints.
- Removed topic: Common Types of Global Constraints.
- Removed topic: Settings That Direct Compilation and Analysis Flows.
- Updated topic: Node, Entity and Instance-Level Constraints.
- Added table: Quartus Prime Tools to Set Node, Entity and Instance Level Constraints.
- Added topic: Assignment Editor.
- Updated topic: Constraining Designs with the Pin Planner.
- Updated topic: Constraining Designs with the Chip Planner.
- Added topic: Constraining designs with the Design Partition Planner.
- Updated topic: Probing Between Components of the Quartus Prime GUI.
- Added example: Locate a Resource Selected in the Project Navigator.
- Updated topic: SDC and the Timing Analyzer, and renamed to Specifying Individual Timing Constraints.
- Added figure: Constraint Menu in Timing Analyzer.
- Added example: Create Clock Dialog Box.
- Updated topic: Constraining Designs with Tcl, and renamed to Constraining Designs with Tcl Scripts
- Updated topic: Quartus Prime Settings Files and Tcl , and renamed to Generating Quartus Prime Settings Files.
- Added example: blinking_led.qsf File.
- Updated topic: Timing Analysis with Synopsys Design Constraints and Tcl, and renamed to Timing Analysis with .sdc Files and Tcl Scripts.
- Added example: .sdc File with Timing Constraints.
- Added topic: Tcl-only Script Flows.
- Updated topic: A Fully Iterative Scripted Flow.
- Removed references to deprecated Fitter Effort logic option.
- Implemented Intel rebranding.
- Changed instances of Quartus II to Intel Quartus Prime.
||Update Pin Planner description for task and report windows.
||Removed survey link.
||Rewrote chapter to more broadly cover all design constraint methods. Removed procedural steps and user interface details, and replaced with links to Quartus II Help.
- Added two notes.
- Minor text edits.
- Revised and reorganized the entire chapter.
- Added section “Probing to Source Design Files and Other Quartus Windows” on page1–2.
- Added description of node type icons (Table1–3).
- Added explanation of wildcard characters.
||Changed to 8½” × 11” page size. No change to content.
||Updated Quartus II software 8.0 revision and date.