Intel® Quartus® Prime Pro Edition User Guide: Design Constraints
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2. Constraining Designs
You can specify design constraints in the GUI, with scripts, or directly in the files that store the constraints. The Intel® Quartus® Prime software preserves the constraints that you specify in the GUI in the following files:
- Intel® Quartus® Prime Settings file (<project_directory>/<revision_name>.qsf)—contains project-wide and instance-level assignments for the current revision of the project, in Tcl syntax. Each revision of a project has a separate .qsf file.
- Synopsys* Design Constraints file (<project_directory>/<revision_name>.sdc)—the Timing Analyzer uses industry-standard Synopsys* Design Constraint format and stores those constraints in .sdc files.
What's New In This Version
- The current version of the Intel® Quartus® Prime Pro Edition software now supports the Hard Memory Network-on-Chip (NoC) for designs targeting Intel Agilex® 7 M-Series FPGAs only. Refer to Interface Planner NoC Tool Flow and Specify NoC Constraints in NoC Assignment Editor.
- The Intel Agilex device family now has multiple members, as this document reflects throughout.