220.127.116.11. Specify Instance-Specific Constraints in Assignment Editor 18.104.22.168. Specify NoC Constraints in NoC Assignment Editor 22.214.171.124. Specify I/O Constraints in Pin Planner 126.96.36.199. Plan Interface Constraints in Interface Planner and Tile Interface Planner 188.8.131.52. Adjust Constraints with the Chip Planner 184.108.40.206. Constraining Designs with the Design Partition Planner
220.127.116.11. Step 1: Setup and Synthesize the Project
Interface Planner requires at least a partially complete, synthesized Intel® Quartus® Prime project as input. You can also use Interface Planner to adjust placement for a fully complete design project.
Follow these steps to setup the project and run synthesis:
- Complete at least the following steps for your design:
- Fully define known device periphery interfaces.
- Instantiate all known interface IP cores.
- Declare all general purpose I/Os.
- Define the I/O standard, voltage, drive strength, and slew rate for all general purpose I/Os.
- Define the core clocking (optional, but recommended).
- Connect all interfaces of the periphery IP to virtual pins or test logic. This technique creates loop backs on any interfaces in the shell design, helping to ensure that periphery interfaces persist after synthesis optimization.
- To synthesize the design, click Processing > Start > Start Analysis & Synthesis. You must run at least Analysis & Synthesis before running Interface Planner.
Did you find the information on this page useful?