3.2.3. Constraining Dynamic Reconfiguration IP
Dynamic reconfiguration allows you to modify some features of an Intel® FPGA IP interface in real time, while the FPGA remains in continuous operation. This dynamic reconfiguration capability allows you to change your design to run at different data rates, and with different features, for different IP "profiles."
When you generate a dynamically reconfigurable IP instance, the IP includes a .mif file that specifies the base and secondary profiles that you define. Each profile contains the delta programming sequences for the dynamic reconfiguration of the IP in a linked-list format.
Did you find the information on this page useful?