Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/03/2023

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Document Table of Contents Step 4: Plan Periphery Placement

Click Plan Design on the Flow control to interactively place IP cores and other design elements in legal locations in the device periphery. The Plan tab displays a list of your project's design elements, alongside a graphical abstraction of the target device architecture.

For efficiency, place design elements in the following order in Interface Planner:

  1. Place all I/O pins or elements, such as PLLs, that have known, specific location requirements.
  2. Place all known periphery interface IP.
  3. (Optional) Place all remaining unplaced cells.

Use the following controls to place design elements in the Interface Planner floorplan:

  1. Locate design elements that you want to place in the Design Element list. You can search and filter the list by name, IP, placement status, I/Os, and other criteria.
  2. To customize design element color coding definitions, click the Highlight column.
    Figure 13.  Interface Planner (Plan Tab)
  3. Use any of the following methods to place design elements in the floorplan:
    • Drag elements from the Design Elements list and drop them onto available device resources in the Chip or Package view. Use Ctrl+Click to drag and pan across the Chip or Package views. You may experience a small delay while dragging as Interface Planner calculates the legal locations.
    • To allow Interface Planner to place an unplaced design element in a legal location, right-click and select Autoplace Selected. You must use Autoplace Selected for all unplaced clocks .
    • Click the button next to the Design Elements to display a list of Legal Locations. Click any legal location in the list to highlight the location in the floorplan. Double-click any location in the list to place the element in the location.
    Figure 14. Listing Legal Locations
  4. To step forward and backward though your plan changes, click the Undo and Redo buttons.
  5. To visualize and traverse design connectivity (for example, to view the reference clock pin and driven destination cells of a PLL), select any design element and then click the Link Info tab. Click the Back and Forward buttons to traverse design connectivity.
  6. To generate a report that shows the placement locations the Fitter prefers, select a design element and click Report Placeability of Selected Element.
Figure 15. Link Info Tab for Traversing Connectivity
Note: Changes made in Interface Planner do not apply to your Intel® Quartus® Prime project until you apply the generated interface plan constraints script to your project.