184.108.40.206. Specify Instance-Specific Constraints in Assignment Editor 220.127.116.11. Specify NoC Constraints in NoC Assignment Editor 18.104.22.168. Specify I/O Constraints in Pin Planner 22.214.171.124. Plan Interface Constraints in Interface Planner and Tile Interface Planner 126.96.36.199. Adjust Constraints with the Chip Planner 188.8.131.52. Constraining Designs with the Design Partition Planner
184.108.40.206. Plan Tab Controls
The Plan tab contains the Design Tree and tile visualization panes. The Design Tree lists design elements for placement. The tile visualization pane displays a graphical view of the target device tile to help you visualize the appropriate legal locations for placement of component IP.
Click Plan Design on the Flow control to display the Plan tab.
|Lists legal locations for placement in the Legal Locations pane.|
|Unplace All||Unplaces all placed design elements in the interface plan.|
|Chip View||Displays the target device at the chip level of detail, showing a representation of the divisions of device resources spread across the device. Zoom in to display chip details.|
|Package View||Displays the target device package at the package level of detail, showing the I/O pin details of the device package. Zoom in to display package details.|
|Birdseye View||Displays the target device chip or package view at maximum Zoom Out.|
|Reset Plan||Unplaces all placed design elements and removes applied project assignments from the tile interface plan.|
|Zoom In and Zoom Out||Increases or decreases the magnification of the tile view to show more or less detail.|
|Fit in Window||Increases or decreases the magnification of the tile view to fit in the current window.|
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