188.8.131.52. Specify Instance-Specific Constraints in Assignment Editor 184.108.40.206. Specify NoC Constraints in NoC Assignment Editor 220.127.116.11. Specify I/O Constraints in Pin Planner 18.104.22.168. Plan Interface Constraints in Interface Planner and Tile Interface Planner 22.214.171.124. Adjust Constraints with the Chip Planner 126.96.36.199. Constraining Designs with the Design Partition Planner
188.8.131.52. Step 6: Run Logic Generation and Design Synthesis
After saving your tile plan assignments, run the Compiler's Logic Generation stage to implement your tile plan and run the remaining design compilation stages.
To run Logic Generation and design synthesis, follow these steps:
- Save your tile interface plan, as Step 5: Save Tile Plan Assignments describes.
- In the Intel® Quartus® Prime software, double-click the Logic Generation stage in the Compilation Dashboard. Logic Generation reads the tile plan assignments from the .qsf.
Figure 44. Run Logic Generation Stage Before Synthesis
- Once Logic Generation completes, double-click Analysis & Synthesis on the dashboard.
- Once Analysis & Synthesis complete, run the other remaining downstream stages in the compilation flow when ready.