Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/03/2023

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Document Table of Contents Step 6: Run Logic Generation and Design Synthesis

After saving your tile plan assignments, run the Compiler's Logic Generation stage to implement your tile plan and run the remaining design compilation stages.
To run Logic Generation and design synthesis, follow these steps:
  1. Save your tile interface plan, as Step 5: Save Tile Plan Assignments describes.
  2. In the Intel® Quartus® Prime software, double-click the Logic Generation stage in the Compilation Dashboard. Logic Generation reads the tile plan assignments from the .qsf.
    Figure 44. Run Logic Generation Stage Before Synthesis
  3. Once Logic Generation completes, double-click Analysis & Synthesis on the dashboard.
  4. Once Analysis & Synthesis complete, run the other remaining downstream stages in the compilation flow when ready.