SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/09/2024
Public
Document Table of Contents

5.4.6. Intel FPGA Video Streaming Interface

This IP can optionally transport video using the Intel FPGA streaming video protocol, which uses the industry standard AXI4-Stream protocol with extensions for transporting metapacket and active video data.

It allows interfacing to Intel FPGA Video and Vision Processing (VVP) Suite IPs or other AXI4-Stream compliant third-party video IPs.

Note: This feature is only available for Agilex™ 7 F-Tile device.
Figure 33. SDI II IP Core with Intel FPGA Video Streaming Interface

When the Enable active video data protocols parameter is set to AXIS-VVP Full, the AXI4-Stream to Clocked Video Converter (AXI2CV) and Clocked Video to AXI4-Stream Converter (CV2AXI) submodules are instantiated as part of the SDI II TX and RX IP subsystem, respectively. The AXI2CV converts the video data from AXI4-Stream format (full variant) to clocked video format while the CV2AXI converts the video data from clocked video format to AXI4-Stream format (full variant).

The Intel FPGA video streaming interface is only available when Video standard parameter is set to “Multi rate (up to 12G-SDI)”. The AXI4-Stream Video In and Out interfaces support 2 pixels in parallel, 3 color planes per pixel and parameterizable 10 and 12 bits per color sample. This means the AXI4-Stream Video In and Out interfaces that running at 300 MHz can support active video resolutions up to 4096x2160 at 60 Hz and chroma sampling formats up to 4:4:4 at 12 bits.