Nios® II Flash Programmer User Guide

ID 683118
Date 11/06/2017
Document Table of Contents

B.5.2. Suggested Actions

  • Reconfigure the FPGA with a valid target design via JTAG using the Intel® Quartus® Prime programmer. If the FPGA is configured by another method, such as by a configuration controller, the pins that connect to the EPCS device might be disabled.
  • If you are using quartus_pgm --nios2 from the command line, ensure you specified the correct base address for your EPCS device. You can find the flash memory's base address in Platform Designer.
  • Ensure that the EPCS device is correctly connected to the FPGA on the board. Verify the EPCS connection by running the "Test EPCS" routine in the "Memory Test" software template provided by the Nios® II EDS. If the test fails, there is a problem with your memory connection. There are two places to look for the problem:
    • The physical connection on your target board
    • The pin assignments on the top-level FPGA design
  • Use the Intel® Quartus® Prime Programmer to program the EPCS device directly via a JTAG download cable, and verify that the EPCS device successfully configures the FPGA.
  • Run quartus_pgm --nios2 from the command line with the --epcs parameter. This command displays information about the flash memory in the EPCS device. For more information, refer to the "Using the Flash Programmer from the Command Line" chapter.