Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Divide-by with -waveform Clock Constraints Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Basic Clock Divider Using -divide_by

You can derive clocks in a design from a clock source when the derived clock is slower than the source clock. When constraining a slower clock derived from a clock source, use the -divide_by option.
Figure 3. Divide-by-Two Derived Clock

Divide-by with -waveform Clock Constraints

create_clock -period 10.000 -name clk [get_ports {clk}]
# Using -divide_by option
create_generated_clock \
	-divide_by 2 \
	-source [get_ports {clk}] \
	-name clkdiv \
	[get_pins {DIV|q}]
# Alternatively use pins to constrain the divider without
# knowing about the original source
create_generated_clock \
	-divide_by 2 \
	-source [get_pins {DIV|clk}] \
	-name clkdiv \
	[get_pins {DIV|q}]
# the second option works since the
# clock pin of the register DIV is
# connected to the same net fed by the
# clock port clk

You can also create a divide-by clock with the -edges option which allows you to specify the rising, falling, and next rising edge for a clock.

Figure 4. Divide-by- Two Clock with the -edges Option

Divide-by with -waveform Clock Constraints

# Edge numbers are based on the master clock
create_generated_clock \
	-edges {1 3 5} \
	-source [get_pins {DIV|clk}] \
	-name clkdiv \
	[get_pins {DIV|q}]
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