Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock Toggle Register Constraints PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Toggle Register Generated Clock

Use a toggle register to create a divide-by-two clock. If the data feeding the toggle register is at a logical “1” value and fed by a 10 ns period clock, the output of the register is a clock with a period of 20 ns.

The constraints for the toggle register clock is very similar to the previous example.

Figure 5. Toggle Register Generating a Divide-by-Two Clock

Toggle Register Constraints

# Create a base clock
create_clock \
	-period 10.000 \
	-name clk \
	[get_ports {clk}]
# Create the generated clock on the output
# of the toggle register.
create_generated_clock \
	-name tff_clk \
	-source [get_ports {clk}] \
	-divide_by 2 \
	[get_pins {tff|q}]
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