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Ixiasoft
System Synchronous Output
The following figure shows a typical chip-to-chip output interface and the various parameters necessary to specify an output delay for the interface.
Figure 13. Simple Chip-to-Chip Interface
System Synchronous Output Constraints
#specify the maximum external clock delay to the FPGA
set CLKs_max 0.200
#specify the minimum external clock delay to the FPGA
set CLKs_min 0.100
#specify the maximum external clock delay to the external device
set CLKd_max 0.200
#specify the minimum external clock delay to the external device
set CLKd_min 0.100
#specify the maximum setup time of the external device
set tSU 0.125
#specify the minimum setup time of the external device
set tH 0.100
#specify the maximum board delay
set BD_max 0.180
#specify the minimum board delay
set BD_min 0.120
#create a clock 10ns
create_clock -period 10 -name sys_clk [get_ports sys_clk]
#create the associated virtual input clock
create_clock -period 10 -name virt_sys_clk
#create the output maximum delay for the data output from the FPGA that #accounts for all delays specified
set_output_delay -clock virt_sys_clk \
-max [expr $CLKs_max + $BD_max + $tSU - $CLKd_min] \
[get_ports {data_out[*]}]
#create the output minimum delay for the data output from the FPGA that #accounts for all delays specified
set_output_delay -clock virt_sys_clk \
-min [expr $CLKs_min + $BD_min - $tH - $CLKd_max] \
[get_ports {data_out[*]}]