Intel® Quartus® Prime Timing Analyzer Cookbook

ID 683081
Date 7/21/2022

Offset Clocks

When you constrain clocks in the Timing Analyzer, the first rising or falling edge of a clock occurs at an absolute 0 by default. You can create an offset for the clock with the -waveform option.
Figure 2. Simple Register-to-Register Path Clocked by clkB

Offset Clock Constraints

# -waveform defaults to 50/50 duty cycle
create_clock -period 10.000 \
	-name clkA \
	[get_ports {clkA}]
#create a clock with a 2.5 ns offset
create_clock -period 10.000 \
	-waveform {2.500 7.500} \
	-name clkB [get_ports {clkB}]