Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions Multicycle Clock-to-Clock Multicycle Register-to-Register False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

Multicycle Exceptions

By default, the Timing Analyzer uses a single-cycle analysis to determine both the setup and hold relationship of any register-to-register path. This single-cycle analysis assumes the most restrictive setup and hold requirements for the circuit. However, you can apply multicycle exceptions to relax the default setup or hold relationship of any register-to-register path when you know this is appropriate for the path.
Figure 15. Register-to-Register Path

You can apply multicycles to clock-to-clock transfers or to individual registers. Applying multicycles to clock-to-clock transfers affects all the specified setup or hold relationships of the target clocks of register-to-register paths fed by the source and destination clocks.

Multicycle Clock-to-Clock

create_clock -period 10 [get_ports clkA]
create_clock -period 5 [get_ports clkB]
set_multicycle_path -from [get_clocks {clkA}] -to [get_clocks {clkB}] -setup -end 2

In the Multicycle Clock-to-Clock example, the setup relationship is relaxed by an additional destination clock period for any register-to-register path where the source clock is clkA and the destination clock is clkB. This results in registers reg1 and reg2 having a setup relationship of 12.5 ns instead of the default 5 ns. The setup relationship between registers reg2 and reg3 is not affected by the multicycle.

Applying multicycles to individual registers affects only the specified registers setup or hold relationship.

In the Multicycle Register-to-Register example in the figure above, the setup relationship is relaxed by an additional destination clock period for the register-to-register path from register reg1 to register reg2. This results in registers reg1 and reg2 having a setup relationship of 10 ns instead of the default 5 ns. The setup relationship between registers reg2 and reg3 is not affected by the multicycle.

Multicycle Register-to-Register

create_clock -period 10 [get_ports clkA]
create_clock -period 5 [get_ports clkB]
set_multicycle_path -from [get_pins {reg1|q}] -to [get_pins {reg2|d}] -setup -end 2
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