Intel® Quartus® Prime Timing Analyzer Cookbook

ID 683081
Date 7/21/2022

Basic Non-50/50 Duty Cycle Clock

The duty cycle of a clock can vary from design to design. The default duty cycle for clocks created in the Timing Analyzer is 50/50. However, you can change the duty cycle of a clock with the -waveform option.
Figure 1. Simple Register-to-Register Path with a 60/40 Duty Cycle Clock

60/40 Duty Cycle Clock Constraint

#60/40 duty cycle clock
create_clock \
	-period 10.000 \
	-waveform {0.000 6.000} \
	-name clk6040 [get_ports {clk}]