Intel® Quartus® Prime Timing Analyzer Cookbook

ID 683081
Date 7/21/2022

Externally Switched Clock

Through an external multiplexer or jumper setting, digital systems are capable of providing different clock frequencies to the same clock port. The Timing Analyzer can model this behavior with the create_clock constraint and the -add option. The following figure shows a simple register-to-register path where you can drive the clock port clock with a 100-MHz clock or a 50-MHz clock.
Figure 8. Simple Register-to-Register Design

Externally Switched Clock Constraints

# The clk port can be driven at 100MHz (10ns) or
# 50MHz (20ns)
# clkA is 10ns
create_clock \
	-period 10.000 \
	-name clkA \
	[get_ports {clk}]
# clkB is 20ns assigned to the same port
# Requires -add option
create_clock \
	-period 20.000 \
	-name clkB \
	[get_ports {clk}] \
set_clock_groups \
	-exclusive \
	-group {clkA} \
	-group {clkB}