Intel® Quartus® Prime Timing Analyzer Cookbook

ID 683081
Date 7/21/2022

PLL Clock Switchover

The PLL can select between two possible input clocks with the PLL clock switchover feature in Intel® FPGAs.
Figure 9. PLL Clock Switchover

PLL Clock Switchover Constraints

#create a 10ns clock for clock port clk0
create_clock \
	-period 10.000 \
	-name clk0 \
	[get_ports {clk0}]
#create a 20ns clock for clock port clk1
create_clock \
	-period 20.000 \
	-name clk1 \
	[get_ports {clk1}]
#automatically create clocks for the PLL output clocks
#derive_pll_clocks automatically makes the proper
#clock assignments for clock-switchover
set_clock_groups \
	-exclusive \
	-group {clk0} \
	-group {clk1}