Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Timing Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover PLL Clock Switchover Constraints
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Timing Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

PLL Clock Switchover

The PLL can select between two possible input clocks with the PLL clock switchover feature in Intel® FPGAs.
Figure 9. PLL Clock Switchover

PLL Clock Switchover Constraints

#create a 10ns clock for clock port clk0
create_clock \
	-period 10.000 \
	-name clk0 \
	[get_ports {clk0}]
#create a 20ns clock for clock port clk1
create_clock \
	-period 20.000 \
	-name clk1 \
	[get_ports {clk1}]
#automatically create clocks for the PLL output clocks
#derive_pll_clocks automatically makes the proper
#clock assignments for clock-switchover
derive_pll_clocks
set_clock_groups \
	-exclusive \
	-group {clk0} \
	-group {clk1}
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