1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board
|Intel® Quartus® Prime Design Suite 19.2|
Incremental block-based compilation enables you to preserve satisfactory compilation results for specific FPGA core logic design blocks (or logic that comprises a hierarchical design instance), and then reuse those results in subsequent compilations. You assign the hierarchical instance as a design partition, which you can then preserve following successful compilation. The preserved design partition must only include core resources (such as LUTs, registers, memory blocks, and DSP blocks), and cannot include any periphery resources.
This tutorial uses an Intel® Arria® 10 design example to show you how to improve the predictability of results and reduce design iterations by:
- Preserving a design partition after synthesis or final compilation, and reusing the preserved results in subsequent compilations.
- Targeting only specific design partitions for optimization, while leaving other design partitions unchanged.
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