AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683079
Date 7/15/2019

1.3. Incremental Block-Based Compilation Tutorial

The steps in this tutorial demonstrate how to improve the predictability of results and reduce design iterations by preserving the successful compilation results of design partitions, and optimizing specific partitions.

Process Description

You determine which design blocks might be suitable for preservation and optimization by running a flat compilation and timing analysis to identify the most timing-critical blocks. You then preserve the partitions for blocks that meet timing, so that the Compiler can reuse the successful results for those partitions in subsequent compilations. When you preserve a partition at the final snapshot, the Compiler preserves the final device resource utilization, placement, routing, and hold time fix-up.

After optimizing the timing-critical design blocks, you can preserve those partitions and focus optimization on other parts of the design.

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