AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683079
Date 7/15/2019

1.3.4. Step 4: Analyze Timing of the Partitioned Design

Follow these steps to analyze the timing of the partitioned design:
  1. Click Tools > Timing Analyzer , and then double-click Update Timing Netlist.
  2. Run the report_timing.tcl script to regenerate the timing analysis reports for failing paths:
    source report_timing.tcl
    The timing analysis reports in the inst_i3 and inst_i4 folders remain red, indicating that u_blinking_led_i3 and u_blinking_led_i4 still do not meet timing requirements in the partitioned design. Later in this tutorial you optimize these design blocks to ensure that they meet timing requirements in the flat design.
    Figure 10. u_blinking_led_i3 and u_blinking_led_i4 Violate Timing Requirements
  3. In the inst_big folder, right-click the Slow 900 mV 100C Model report, and then click Generate in All Corners. Repeat this step for the inst_big1_path1, inst_i1_path1, and inst_i2_path1 folders.
  4. View the Multi Corner Summary reports in the inst_big1_path1, inst_i1_path1, and inst_i2_path1 timing analysis folders. The report_timing.tcl script includes commands to generate these reports for pre-selected nodes. Note the slack and placement results for the paths in 3 partitions, as the following figure shows. Later in the tutorial you compare these results with those after compilation of the final snapshot.
    Figure 11. Multi Corner Summary for u_big_partition1_top