AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683079
Date 7/15/2019
Public

1.3.6. Step 6: Optimize Timing-Critical Design Blocks

Follow these steps to optimize the 64-bit counters in blinking_led_8s.sv and blinking_led_16s.sv to improve timing. These changes implement 32-bit addition, rather than 64-bit addition in the counters.
  1. Open blinking_led_8s.sv in a text editor and uncomment the following lines:
        //reg [31:0] count_msb;
        //reg [31:0] count_lsb;
        //reg [1:0] state=2'b00;
        //always_ff @(posedge fast_clock) begin
        //    fifo_wreq <= 1'b0;	       
        //    case (state)
        //        2'b00: begin
        //            count_lsb <= count_lsb + 1;		  
        //            if (count_lsb[31:0]==32'hFFFFFFFF) begin
        //                state <= 2'b01;	      
        //            end
        //        end
        //        
        //        2'b01: begin
        //            count_lsb <= count_lsb + 1;	   
        //            if (count_lsb[31:0]==32'h064962EC) begin	   	   
        //                count_lsb <= 1;		
        //                value_in <= !value_in;
        //                fifo_wreq <= 1'b1;
        //                state <= 2'b00;
        //            end
        //        end
        //        
        //        default: begin
        //            count_msb <= 0;			
        //            count_lsb <= 0;
        //            state <= 2'b00;
        //        end        	
        //    endcase   
        //end
  2. In blinking_led_8s.sv, comment the following lines and save the changes:
        reg [63:0] count_in;
        always_ff @(posedge fast_clock) begin
            count_in <= count_in + 1;
            fifo_wreq <= 1'b0;      
            if (count_in==64'd4400440044) begin
                count_in <= 0;
                value_in <= !value_in;	 
                fifo_wreq <= 1'b1;
            end
        end
  3. Open blinking_led_16s.sv and uncomment the following lines:
        //reg [31:0] count_msb;
        //reg [31:0] count_lsb;
        //reg [1:0] state=2'b00;
        //
        //always_ff @(posedge fast_clock) begin
        //    fifo_wreq <= 1'b0;	       
        //    
        //    case (state)
        //    2'b00: begin
        //        count_lsb <= count_lsb + 1;		  
        //        if (count_lsb[31:0]==32'hFFFFFFFF) begin
        //            state <= 2'b01;	      
        //        end
        //    end
        //    
        //    2'b01: begin
        //       count_lsb <= count_lsb + 1;
        //       if (count_lsb[31:0]==32'hFFFFFFFF) begin	   
        //           state <= 2'b10;	      
        //       end
        //    end	
        //    
        //    2'b10: begin
        //       count_lsb <= count_lsb + 1;	   
        //       if (count_lsb[31:0]==32'h0C92C5D8) begin	   	   
        //           count_lsb <= 1;	      
        //           value_in <= !value_in;
        //           fifo_wreq <= 1'b1;
        //           state <= 2'b00;
        //       end
        //    end
        //    
        //    default: begin
        //        count_msb <= 0;			
        //        count_lsb <= 0;
        //        state <= 2'b00;
        //    end
        //    
        //    endcase
        //end
  4. In blinking_led_16s.sv, comment the following lines and save the changes:
        reg [63:0] count_in;
        always_ff @(posedge fast_clock) begin
            count_in <= count_in + 1;
            fifo_wreq <= 1'b0;
            if (count_in==64'd8800880088) begin							   
                count_in <= 0;
                value_in <= !value_in;
                fifo_wreq <= 1'b1;
            end	
        end
  5. To compile the design with these changes, click Compile Design on the Compilation Dashboard.