AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

ID 683079
Date 7/15/2019

1.1. Tutorial Design Overview

This tutorial includes a prepared design example to demonstrate incremental block-based compilation. You can download the design example to follow along with the tutorial steps in the Intel® Quartus® Prime Pro Edition software, as Downloading Tutorial Design Files describes.

The example top-level design instantiates a PLL that generates a 550 MHz fast clock (CLK1), and a 100 MHz slow clock (CLK2). The top-level design also instantiates 4 blinking LED modules that drive LED[3:0] every 2, 4, 8, and 16 seconds, respectively.

Figure 1. Incremental Block-Based Compilation Tutorial Design Example

To increase the design size in the Intel® FPGA, the design example also instantiates 20 duplicate instances of an OpenCores* design.1

The duplicate OpenCores* design instances have the following characteristics:

  • The design implements each instance in parallel.
  • I/O wrapper logic is present to reduce the number of I/O pins that the larger design requires.
  • No timing-critical paths exist between the instances and the wrapper logic.