AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683079
Date 7/15/2019
Public
Document Table of Contents
Document Table of Contents x
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Incremental Block-Based Compilation Tutorial Revision History
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board

1.3.9. (Optional) Step 9: Verify Results in Hardware

After device programming you can verify the results of this tutorial in hardware. After completing this tutorial, LEDs D6-D3 map to the blinking_led_top instance, and LEDs D10-D7 map to the top-level design. After you configure the FPGA with the SRAM Object File (.sof), blinking_led flashes red LEDs in the following order:

  1. D3 blinks every two seconds
  2. D4 blinks every four seconds
  3. D5 blinks every eight seconds
  4. D6 blinks every 16 seconds

The top-level design illuminates LEDs D10-D7 as a shifting bit in green.

Figure 21. Illumination of LEDs during Hardware Verification
Level Two Title

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